1. Field of the Invention
The present invention relates generally to wafer processing. More particularly, the present invention relates to an improved wafer back side grinding process.
2. Description of the Prior Art
Three-dimensional (3D) integration is an emerging technology to increase performance and functionality of integrated circuits. Presently 3D die stacking is achieved by wire bonding of stacked die or bumped stack die technologies. The Through-Silicon-Via (TSV) stacked die concept is an emerging technology which requires wafer-to-wafer or wafer-to-support system (carrier) bonding.
By using TSV technology, 3D ICs can pack a great deal of functionality into a small footprint. In addition, critical electrical paths through the device can be drastically shortened, leading to faster operation and better performance.
After TSV process, the wafer is ordinarily subjected to wafer thinning or wafer back side grinding process in order to reduce the thickness of the wafer. However, the conventional wafer back side grinding process has several drawbacks. For example, the conventional wafer back side grinding process has low throughput because the wafer support system (WSS) typically handles one piece of wafer at one time. The conventional wafer support system typically requires a silicon or glass carrier that adds production expense.
Therefore, there is a need in this industry to provide an improved wafer thinning or wafer back side grinding process, which is cost-effective and provides high throughput and reduced process time per wafer.